5M1270ZT144C5N

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1. Describe

Compared with other CPLDs, MAX® V series low-cost and low-power CPLDs provide higher density and I/O per footprint. The density of MAX V devices ranges from 40 to 2,210 logic elements (LE) (32 to 1,700 equivalent macrocells) and up to 271 I/Os Programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring and control, FPGA configuration, and analog I2C interfaces. MAX V devices have on-chip flash memory, internal oscillator, and memory functions. The total power consumption of MAX V CPLDs is up to 50% lower than other CPLDs, and only one power supply is required to help you meet low-power design requirements.

2. Feature

    1. Low-cost, low-power, and non-volatile CPLD architecture

    2. Instant-on (0.5 ms or less) configuration time

    3. Standby current as low as 25 µA and fast power-down/reset operation

    4. Fast propagation delay and clock-to-output times

    5. Internal oscillator

    6. Emulated RSDS output support with a data rate of up to 200 Mbps

    7. Emulated LVDS output support with a data rate of up to 304 Mbps

    8. Four global clocks with two clocks available per logic array block (LAB)

    9. User flash memory block up to 8 Kbits for non-volatile storage with up to 1000 read/write cycles

  10. Single 1.8-V external supply for device core

  11. MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels

  12. Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors

  13. Schmitt triggers enabling noise tolerant inputs (programmable per pin)

  14. I/Os are fully compliant with the PCI-SIG® PCI Local Bus Specification, revision 2.2 for 3.3-V operation

  15. Hot-socket compliant

  16. Built-in JTAG BST circuitry compliant with IEEE Std. 

3. Functional Description

Mtecture to implement custom logic. Row and column interconnects provide signal inteAX V devices contain a two-dimensional row- and column-based archirconnects between the logic array blocks (LABs). Each LAB in the logic array contains 10 logic elements (LEs). An LE is a small unit of logic that provides efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The MultiTrack interconnect provides fast granular timing delays between LABs. The fast routing between LEs provides minimum timing delay for added levels of logic versus globally routed interconnect structures. The I/O elements (IOEs) located after the LAB rows and columns around the periphery of the MAX V device feeds the I/O pins. Each IOE contains a bidirectional I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs and various single ended standards, such as 33-MHz, 32-bit PCI™, and LVTTL. MAX V devices provide a global clock network. The global clock network consists of four global clock lines that drive throughout the entire device, providing clocks for all resources within the device. You can also use the global clock lines for control signals such as clear, preset, or output enable.

4. Parallel interface

This interface allows parallel communication logic between the UFM module and the outside. After the READ request, WRITE request, or ERASE request is asserted (active low assertion), the external logic or device (such as a microcontroller) can continue the operation when the data in its UFM is retrieved, written or erased. During this time, the nBUSY signal is driven to "low" to indicate that it cannot respond to any Further requests. After the operation is completed, bringing the nBUSY signal back to "High" means that the new request can now be serviced. If it is a read request, DATA_VALID is driven to "high" to indicate that the data on the DO port is valid data from the last read address. It is not allowed to assert READ, WRITE, and ERASE at the same time. Multiple requests were ignored, and nothing was read, written, or erased in the UFM block. There is no support for sequential reads and page writes in the parallel interface. For both read-only and parallel interface read/write modes, OSC_ENA is always set to enable the internal oscillator.