AT25080AN-10SU-1.8

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1. Description

The AT25080AN-10SU-1.8/160A/320A/640A provides 8192/16384/32768/65536 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25080A/160A/320A/640A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8- lead TSSOP and 8-Lead Ultra Leadframe Land Grid Array (ULLGA) packages. The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate erase cycle is required before write.

2. Features

    1. Serial Peripheral Interface (SPI) Compatible

    2. Supports SPI Modes 0 (0,0) and 3 (1,1)

        – Datasheet Describes Mode 0 Operation

    3. Low-voltage and Standard-voltage Operation

        – 2.7 (VCC = 2.7V to 5.5V)

        – 1.8 (VCC = 1.8V to 5.5V)

    4. 20 MHz Clock Rate (5V)

    5. 32-byte Page Mode

    6. Block Write Protection

        – Protect 1/4, 1/2, or Entire Array

    7. Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection

    8. Self-timed Write Cycle (5 ms max)

    9. High Reliability

        – Endurance: One Million Write Cycles

        – Data Retention: 100 Years

  10. Available in Automotive

  11. 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead MAP, 8-lead Ultra Thin Mini-MAP (MLP 2x3) and 8-lead TSSOP Packages

  12. Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers

3. Pin Configuration

4. Pin description

5. Serial Interface Description

    1. MASTER: The device that generates the serial clock.

    2. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080A/160A/320A/640A always operates as a slave.

    3. TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated for data transmission (SO) and reception (SI).

    4. MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.

    5. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed.

    6. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication.

    7. CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.

    8. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high

impedance state.

    9. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25080A/160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.