AT45DB321E-SHF-B

Description

Adesto®AT45DB321E is the lowest 2.3V serial interface serial access flash memory, which is very suitable for various digital voice, image, program code and data storage applications. AT45DB321E also supports RapidS serial interface, suitable for applications that require very high-speed operation. Its 34,603,008-bit memory is divided into 8,192 pages in the following way, each page has 512 bytes or 528 bytes. In addition to the main memory, the AT45DB321E also contains two SRAM buffers of 512/528 bytes. When a page is received in the main memory, this buffer allows reprogramming of the received data. Interleaving between the two buffers can significantly improve the system's ability to write continuous data flow. In addition, the SRAM buffer can be used as an additional system scratchpad and E2 PROM emulation (changeability of bits or bytes) can be easily handled through independent three-step read-modify-write operations.

Unlike traditional flash memory, traditional flash memory is randomly accessed through multiple address lines and parallel interfaces.

AdestoDataFlash® uses a serial interface to access its data sequentially. Simple sequential access can significantly reduce the number of effective pins, simplify simplified hardware layout, improve system reliability, minimize switching noise, and reduce package size. The device is optimized for many commercial and industrial applications that require high density, low pin count, low voltage and low power consumption.

In order to realize the simple reprogrammability in the system, AT45DB321E does not need to program the high input voltage. The device uses a single 2.3V to 3.6V power supply for erasing, programming and reading

operating. AT45DB321E is enabled through the chip select pin (CS) and accessed through the 3-wire interface The relationship between serial input (SI), serial output (SO) and serial clock (SCK).

All program and erase cycles are self-timed.

Features 

   1. Single 2.3V - 3.6V supply 

   2. Serial Peripheral Interface (SPI) compatible

   3. Continuous read capability through entire array

   4. User configurable page size

   5. Two fully independent SRAM data buffers (512/528 bytes) 

   6. Flexible programming options

   7. Flexible erase options

   8. Program and Erase Suspend/Resume 

   9. Advanced hardware and software data protection features

 10. 128-byte, One-Time Programmable (OTP) Security Register

 11. Hardware and software controlled reset options 

 12. JEDEC Standard Manufacturer and Device ID Read 

 13. Low-power dissipation

 14. Endurance: 100,000 program/erase cycles per page minimum 

 15. Data retention: 20 years 

 16. Green (Pb/Halide-free/RoHS compliant) packaging options

Pin Configurations and Pinouts

Operation Mode Summary

1. Group A commands include:

    1. Main memory page read

    2. Continuous array read (SPI)

    3. Read the sector protection register

    4. Read sector lock register

    5. Read the security registration

    6. Buffer 1 (or 2) read

2. Group B commands include:

    1. Page erase

    2. Block erase

    3. Sector Erase

    4. Chip erase

    5. Transfer of main memory page to buffer 1 (or 2)

    6. Compare the main memory page to buffer 1 (or 2)

    7. Buffer 1 (or 2) with built-in erasing function to the main memory page program

    8. Buffer 1 (or 2) to the main memory page program, no built-in erasure

    9. Main memory page program of buffer 1 (or 2) with built-in erasing function

  10. Main memory byte/page program through buffer 1, no built-in erasure

  11. Automatic page rewriting

3. Group C commands include:

    1. Buffer 1 (or 2) write

    2. Status register read

    3. Read manufacturer and device ID

4. Group D commands include:

    1. Erase sector protection register

    2. Planning department protection register

    3. Department lock

    4. Program Security Register

    5. Buffer and page size configuration

    6. Freeze department lock