• Manufacturer Part# BR24T64FJ-WE2
  • Product CategoryIntegrated Circuits (ICs)
  • Short DescriptionIC EEPROM 64K I2C 400KHZ 8SOPJEEPROM Memory IC 64K...
  • More DetailN/A
In Stock: 9514

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Technical Details

  • Series:BR24T64-W
  • Packaging:Tape & Reel (TR) 
  • Part Status:Active
  • Memory Type:Non-Volatile
  • Memory Format:EEPROM
  • Technology:EEPROM
  • Memory Size:64Kb (8K x 8)
  • Clock Frequency:400kHz
  • Write Cycle Time - Word, Page:5ms

 

  • Access Time:--
  • Memory Interface:I²C
  • Voltage - Supply:1.6 V ~ 5.5 V
  • Operating Temperature:-40°C ~ 85°C (TA)
  • Mounting Type:Surface Mount
  • Package / Case:8-SOIC (0.154", 3.90mm Width)
  • Supplier Device Package:8-SOP-J
  • Base Part Number:BR24T64

Description

1. I2C BUS Data CommunicationI 2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte.     I2C BUS data communication with several devices is possible by connecting with 2 communication lines: serial data (SDA) and serial clock (SCL). Among the devices, there should be a “master” that generates clock and control communication start and end. The rest become “slave”which are controlled by an address peculiar to each device, like this EEPROM. The device that outputs data to the bus during data communication is called“transmitter”, and the device that receives data is called “receiver”..

2. Start Condition (Start Bit Recognition)

   (1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary.

   (2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command cannot be executed.

3. Stop Condition (Stop Bit Recongition)

   (1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is 'HIGH'.

4. Acknowledge (ACK) Signal

  (1) The acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In a master-slave communication, the device (Ex. µ-COM sends slave address input for write or read command, to this IC ) at the transmitter (sending) side releases the bus after output of 8bit data.

  (2) The device (Ex. This IC receives the slave address input for write or read command from the µ-COM) at the receiver (receiving) side sets SDA 'LOW' during the 9th clock cycle, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data.

  (3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.

  (4) After receiving 8bit data (word address and write data) during each write operation, this IC outputs acknowledge signal(ACK signal) 'LOW'.

  (5) During read operation, this IC outputs 8bit data (read data) and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC continues to output data. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer,recognizes stop condition (stop bit), and ends read operation. Then this IC becomes ready for another transmission.

Features

 1. Completely conforming to the world standard I2CBUS.

     All controls available by 2 ports of serial clock (SCL) and serial data (SDA)

 2. Other devices than EEPROM can be connected to the same port, saving microcontroller port

 3. 1.6V to 5.5V Single Power Source Operation most suitable for battery use

 4. 1.6V to 5.5V wide limit of operation voltage, possible FAST MODE 400KHz operation

 5. Page Write Mode useful for initial value write at 

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