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1. Describe
CAT24C512WI-G is an internal EERPOM serial 512−Kb I2C Organized into 65,536 words of 8 bits each. It has a 128-byte page write buffer and supports standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocols. Write operations can be disabled by pulling the WP pin high (this protect the entire memory). External address pins can address up to 8 CAT24C512 devices are on the same bus. On-chip ECC (Error Correcting Code) makes the device suitable for For high reliability applications.
2. Feature
1. Supports Standard, Fast and Fast-Plus I2C protocols
2. 1.8 V to 5.5 V supply voltage range
3. 128-byte page write buffer
4. Hardware write protection of entire memory
5. Schmitt trigger and noise suppression filter on I2C bus input (SCL and SDA)
6. Low power CMOS technology
7. 1,000,000 program/erase cycles
8. 100-year data retention
9. Industrial and extended temperature range
10. 8-pin, SOIC, TSSOP, 8-pad UDFN and 8-ball WLCSP packages
11. These devices are lead-free, halogen-free/BFR-free, and RoHS compliant
3. Pin configuration
4. Pin Description
5. Function Description
CAT24C512 supports inter-IC (I2C) bus data transfer protocol, which defines a device Send data to the bus as a transmitter and as a device Receive data as a receiver. Data flow is controlled by a master device, which generates the serial clock and all start and stop conditions. The CAT24C512 acts as slave device. master-slave alternation transmitter or receiver. Connect up to 8 devices The bus is input by the device address A0, A1, and A2
