CPC7591BA

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1. Description

The CPC7591BA  is a member of IXYS Integrated Circuits Division’s next generation Line Card Access Switch (LCAS) family. This monolithic 4-pole solid state switch is available in a 16-pin SOIC package. It provides the necessary functions to replace the 2-Form-C electromechanical ringing relay and it’s associated snubber circuitry on traditional analog line cards or contemporary integrated voice and data (IVD) line cards found in Central Office (CO), Access, and PBX equipment. Because this device contains solid state switches for tip and ring line break and for ringing injection/return, it requires only a +5 V supply for operation and TTL logic-level inputs for control. The CPC7591 provides stable start-up conditioning during system power up and for hot plug insertion applications. Once active, the inputs respond to traditional TTL logic levels, enabling the CPC7591 to be used with 3.3V-only logic. For negative transient voltage protection the CPC7591BA version includes SCRs to provide voltage fold-back protection for the SLIC and subsequent circuitry, while the CPC7591BB version utilizes clamping diodes to the VBAT pin. For positive transient voltage protection all versions provide clamping diodes to the FGND pin.

2. Features

    1. TTL Logic Level Inputs for 3.3V Logic Interfaces

    2. Smart Logic for Power Up / Hot Plug State Control

    3. Improved Switch dV/dt Immunity of 500 V/s

    4. Monolithic IC Reliability

    5. Low, Matched RON

    6. Eliminates the Need for Zero-Cross Switching

    7. Flexible Switch Timing for Transition from Ringing Mode to Idle/Talk Mode.

    8. Clean, Bounce-Free Switching

    9. Tertiary Protection Consisting of Integrated Current Limiting, Voltage Clamping, and Thermal Shutdown for SLIC Protection

  10. 5V Operation with Power Consumption < 10 mW

  11. Intelligent Battery Monitor

  12. Latched Logic-Level Inputs, no External Drive Circuitry

  13. Small 16-pin SOIC

3. Applications

    1. VoIP Gateways

    2. Central office (CO)

    3. Digital Loop Carrier (DLC)

    4. PBX Systems

    5. Digitally Added Main Line (DAML)

    6. Hybrid Fiber Coax (HFC)

    7. Fiber in the Loop (FITL)

    8. Pair Gain System

    9. Channel Banks

4. Pin configuration

5. Pin description

6. Functional Description

 1. Introduction

Smart logic in the CPC7591 now provides for switch state control during both power up and power loss transitions. An internal detector is used to evaluate the VDD supply to determine when to de-assert the under voltage switch lock out circuitry with a rising VDD and when to assert the under voltage switch lock out circuitry with a falling VDD. Any time unsatisfactory low VDD conditions exist, the lock out circuit overrides user switch control by blocking the information at the external input pins and conditioning internal switch commands to the all-off state. Upon restoration of VDD, the switches will remain in the all-off state until the LATCH input is pulled low.

 2. Switch Timing

The CPC7591 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the break switches SW1 and SW2 using simple TTL logic-level inputs. The two available techniques are referred to as make-before-break and break-before-make operation. When the switch contacts of SW1 and SW2 are closed (made) before the ringing switch contacts of SW3 and SW4 are opened (broken), this is referred to as make-before-break operation. Break-before-make operation occurs when the ringing contacts of SW3 and SW4 are opened (broken) before the switch contacts of SW1 and SW2 are closed (made). With the CPC7591, make-before-break and break-before-make operations can easily be accomplished by applying the proper sequence of TTL logic-level inputs to the device.

 3. Make-Before-Break Operation

To use make-before-break operation, change the logic inputs from the ringing state directly to the talk state. Application of the talk state opens the ringing return switch, SW3, as the break switches SW1 and SW2 close. The ringing switch, SW4, remains closed until the next zero-crossing of the ringing current. While in the make-before-break state, ringing potentials in excess of the CPC7591 protection circuitry thresholds will be diverted away from the SLIC. 

 4. Data Latch

The CPC7591 has an integrated transparent data latch. The latch enable operation is controlled by TTL logic input levels at the LATCH pin. Data input to the latch is via the input pin INRINGING, while the output of the data latch are internal nodes used for state control. When the LATCH enable control pin is at logic 0 the data latch is transparent and the INRINGING input data control signal flows directly through the data latch to the state control circuitry. A change in INRINGING input will be reflected by a change in switch state. Whenever the LATCH enable control pin is at logic 1, the data latch is active and data is locked. Subsequent INRINGING input changes will not result in a change to the control logic or affect the existing switch state. The switches will remain in the state they were in when the LATCH pin changes from logic 0 to logic 1 and will not respond to changes in input as long as the LATCH is at logic 1. However, neither the TSD input nor the TSD output control functions are affected by the latch function. Since internal thermal shutdown control and external“All-off”control is not affected by the state of the LATCH enable input, TSD will override state control.

 5. Pin Description

The TSD pin is a bi-directional I/O structure with an internal pull-up current source with a nominal value of 16 µA biased from VDD. As an output, this pin indicates the status of the thermal shutdown circuitry. Typically, during normal operation, this pin will be pulled up to VDD but under fault conditions that create excess thermal loading the CPC7591 will enter thermal shutdown and a logic low will be output. As an input, the TSD pin is utilized to place the CPC7591 into the “All-Off” state by simply pulling the input low. For applications using low-voltage logic devices (lower than VDD), IXYS IC Division recommends the use of an open-collector or an open-drain type output to control TSD. This avoids sinking the TSD pull up bias current to ground during normal operation when the all-off state is not required. An open-collector or open-drain type device is recommended to drive this pin.

 6. Power Supplies

Both a +5 V supply and battery voltage are connected to the CPC7591. Switch state control is powered exclusively by the +5 V supply. As a result, the CPC7591 exhibits extremely low power consumption during active and idle states. Although battery power is not used for switch control, it is required to supply trigger current for the integrated internal protection circuitry SCR during fault conditions. This integrated SCR is designed to activate whenever the voltage at TBAT or RBAT drops 2 to 4 V below the applied voltage on the VBAT pin. Because the battery supply at this pin is required to source trigger current during negative overvoltage fault conditions at tip and ring, it is important that the net supplying this current be a low impedance path for high speed transients such as lightning. This will permit trigger currents to flow enabling the SCR to activate and thereby prevent a fault induced negative overvoltage event at the TBAT or RBAT nodes.

 7. External Protection Elements

The CPC7591 requires only over voltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for additional external protection on the SLIC side. The secondary protector must limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7591. A foldback or crowbar type protector is recommended to minimize stresses on the CPC7591.