IS25LP016D-JNLE

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1. Describe

IS25LP016D-JNLE and IS25WP016D serial flash memory provide high flexibility and Simplified pin count package performance. ISSI's "Industry Standard Serial Interface" flash memory is suitable for the following systems: Requires limited space, low pin count, and low power consumption. The device is accessed via 4-wire SPI Interface composed of serial data input (SI), serial data output (SO), serial clock (SCK) and chip enable (CE#) pin can also be configured as multiple I/O. The device supports dual and quad I/O as well as standard, dual output and quad output SPI. Clock frequency The frequency of up to 133MHz allows an equivalent clock rate of up to 532MHz (133MHz x 4), which is equivalent to 66Mbytes/s Data throughput. IS25xP series flash memory adds support for DTR (dual transfer rate) commands Address and read data on both edges of the clock. These transfer rates can outperform 16-bit parallel flash The memory allows efficient memory access to support XIP (execute in place) operations. The initial state of the memory array is erased at the factory (all bits are set to 1). QPI (Quad Peripheral Interface) supports 2-cycle instructions to further reduce instruction time. Page can Erase 4 KB sectors, 32 KB blocks, 64 KB blocks, and/or the entire chip as a group. Unified department And block architecture allows a high degree of flexibility, so the device can be used in a wide variety of Applications that require reliable data retention.

2. FEATURES

    1. Industry Standard Serial Interface

        - IS25LP016D: 16Mbit/2Mbyte

        - IS25WP016D: 16Mbit/2Mbyte

        - 256 bytes per Programmable Page

        - Supports standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI

        - Supports Serial Flash Discoverable Parameters (SFDP)

    2. High Performance Serial Flash (SPI)

        - 50MHz Normal and 133Mhz Fast Read

        - 532 MHz equivalent QPI

        - DTR (Dual Transfer Rate) up to 66MHz

        - Selectable Dummy Cycles

        - Configurable Drive Strength

        - Supports SPI Modes 0 and 3

        - More than 100,000 Erase/Program Cycles

        - More than 20-year Data Retention

    3. Flexible & Efficient Memory Architecture

        - Chip Erase with Uniform: Sector/Block Erase (4/32/64 Kbyte)

        - Program 1 to 256 Bytes per Page

        - Program/Erase Suspend & Resume

    4. Efficient Read and Program modes

        - Low Instruction Overhead Operations

        - Continuous Read 8/16/32/64-Byte Burst Wrap

        - Selectable Burst Length

        - QPI for Reduced Instruction Overhead

        - AutoBoot Operation

    5. Low Power with Wide Temp. Ranges

        - Single Voltage Supply

              IS25LP: 2.30V to 3.60V

              IS25WP: 1.65V to 1.95V

        - 4 mA Active Read Current (typ.)

        - 5 µA Standby Current (typ.)

        - 1 µA Deep Power Down (typ.)

        - Temp Grades:

           Extended: -40°C to +105°C

           Auto Grade (A3): -40°C to +125°C

    6. Advanced Security Protection

        - Software and Hardware Write Protection

        - Power Supply Lock Protect

        - 4x256-Byte Dedicated Security Area with OTP User-lockable Bits

        - 128 bit Unique ID for Each Device (Call Factory)

    7. Industry Standard Pin-out & Packages(1,2)

        - B = 8-pin SOIC 208mil

        - N = 8-pin SOIC 150mil

        - V = 8-pin VVSOP 150mil

        - K = 8-contact WSON 6x5mm

        - U = 8-contact USON 2x3mm

        - T = 8-contact USON 4x3mm

        - M = 16-pin SOIC 300mil (Call Factory)

        - L = 8-contact WSON 8x6mm

        - G= 24-ball TFBGA 6x8mm 4x6(Call Factory)

        - H = 24-ball TFBGA 6x8mm 5x5 (Call Factory)

        - KGD (Call Factory)

3. PIN CONFIGURATION

4. Standard SPI

In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions, addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the status of the device. This device supports SPI bus operation modes (0, 0) and (1, 1).

5. Multi I/O SPI

Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.

6. QPI

The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used to switch between these two modes, regardless of the non-volatible Quad Enable (QE) bit status in the Status Register. Power Reset or Software Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode.

7. DTR

In addition to SPI and QPI features, the device also supports Fast READ DTR operation. Fast READ DTR operation allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles by half.