LC4256V-75TN144C

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   brenda@hongda-ic.com

1. Describe

Lattice's high-performance ispMACH 4000 series provides SuperFAST CPLD solutions. The family is a hybrid of Lattice's two most popular architectures: ispLSI® 2000 and ispMACH 4A. Keep the essence of the two families, The ispMACH 4000 architecture focuses on major innovations, combining the highest performance with low Powerful features in the flexible CPLD series. ispMACH 4000 combines high speed and low power consumption with the flexibility required for easy design. Instead of Powerful global routing pool and output routing pool, the series provides excellent first adaptation, timing predictability, routing, pin retention and density migration. The ispMACH 4000 series offers a density of 32 to 512 macrocells. Thin Quad Flat Package (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages have multiple density I/O combinations ranging from 44 to 256 pins/ball. Table 1 shows the macrocell, package and I/O options, and other key parameters. The ispMACH 4000 series has enhanced system integration functions. Support 3.3V (4000V), 2.5V (4000B) And 1.8 V (4000C/Z) power supply voltage and 3.3 V, 2.5 V and 1.8 V interface voltage. In addition, the input can be When the I/O bank is configured for 3.3 V operation, it is safe to drive to 5.5 V, so that the series can withstand 5 V. this ispMACH 4000 also provides enhanced I/O functions, such as slew rate control, PCI compatibility, bus keeper latch, Pull-up resistor, pull-down resistor, open-drain output and hot swap. ispMACH 4000 family member It is programmable in the 3.3 V/2.5 V/1.8 V system through the IEEE standard 1532 interface. The IEEE standard 1149.1 boundary scan test function also allows product testing on automatic test equipment.

2. High Performance

    1. fMAX = 400 MHz maximum operating frequency

    2. tPD = 2.5 ns propagation delay 

    3. Up to four global clock pins with programmable clock polarity control

    4. Up to 80 PTs per output

3. Ease of Design

    1. Enhanced macrocells with individual clock, reset, preset and clock enable controls

    2. Up to four global OE controls

    3. Individual local OE control per I/O pin

    4. Excellent First-Time-FitTM and refit

    5. Fast path, SpeedLockingTM Path, and wide-PT path

    6. Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders

4. Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)

    1. Typical static current 10 µA (4032Z)

    2. Typical static current 1.3 mA (4000C)

    3. 1.8 V core low dynamic power

    4. ispMACH 4000Z operational down to 1.6 V VCC

5. Broad Device Offering

    1. Multiple temperature range support

        – Commercial: 0 to 90 °C junction (Tj)

        – Industrial: –40 to 105 °C junction (Tj)

        – Extended: –40 to 130 °C junction (Tj)

    2. For AEC-Q100 compliant devices, refer to LA-ispMACH 4000V/Z Automotive Data Sheet

6. Easy System Integration

    1. Superior solution for power sensitive consumer applications

    2. Operation with 3.3 V, 2.5 V or 1.8 V LVCMOS I/O

    3. Operation with 3.3 V (4000V), 2.5 V (4000B) or 1.8 V (4000C/Z) supplies

    4. 5 V tolerant I/O for LVCMOS 3.3, LVTTL, and  PCI interfaces

    5. Hot-socketing

    6. Open-drain capability

    7. Input pull-up, pull-down or bus-keeper

    8. Programmable output slew rate

    9. 3.3 V PCI compatible

  10. IEEE 1149.1 boundary scan testable

  11. 3.3 V/2.5 V/1.8 V In-System Programmable (ISP™) using IEEE 1532 compliant interface

  12. I/O pins with fast setup path 

  13. Lead-free package options

7. Enhanced Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms. The software automatically considers the availability and distribution of product term clusters as it fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for increased performance. The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:

    1. Product Term Allocator

    2. Cluster Allocator

    3. Wide Steering Logic

8. Enhanced Clock Multiplexer 

The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The eight sources for the clock multiplexer are as follows:

    1. Block CLK0

    2. Block CLK1

    3. Block CLK2

    4. Block CLK3

    5. PT Clock

    6. PT Clock Inverted

    7. Shared PT Clock

    8. Ground

9. Clock Enable Multiplexer

    Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the following four sources:

    1. PT Initialization/CE

    2. PT Initialization/CE Inverted

    3. Shared PT Clock

    4. Logic High