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1. Description
The LMX2582 device is a low-noise, wideband RF PLL with integrated VCO that supports a frequency range from 20 MHz to 5.5 GHz. The device supports both fractional-N and integer-N modes, with a 32-bit fractional divider allowing fine frequency selection. Integrated noise of 47 fs for 1.8-GHz output makes it an ideal low-noise source. Combining best-in-class PLL and integrated VCO noise with integrated LDOs, this device removes the need for multiple discrete devices in high performance systems. The device accepts input frequencies up to 1.4 GHz, which combined with frequency dividers and programmable low noise multiplier allows flexible frequency planning. The additional programmable low-noise multiplier lets users mitigate the impact of integer boundary spurs. In Fractional-N mode, the device can adjust the output phase by a 32-bit resolution. For applications that need fast frequency changes, the device supports a fast calibration option which takes less than 25 µs. This performance is achieved by using single 3.3-V supply. It supports 2 flexible differential outputs that can be configured as single-ended outputs as well. Users can choose to program one output from the VCO and the second from the channel divider. When not being used, each output can be muted separately.
2. Features
1. Output Frequency Range from 20 to 5500 MHz
2. Industry Leading Phase Noise Performance
– VCO Phase Noise: –144.5 dBc/Hz at 1-MHz Offset for 1.8-GHz Output
– Normalized PLL Noise Floor: –231 dBc/Hz
– Normalized PLL Flicker Noise: –126 dBc/Hz
– 47-fs RMS Jitter (12 kHz to 20 MHz) for 1.8 GHz Output
3. Input Clock Frequency Up to 1400 MHz
4. Phase Detector Frequency Up to 200 MHz, and Up to 400 MHz in Integer-N Mode
5. Supports Fractional-N and Integer-N Modes
6. Dual Differential Outputs
7. Innovative Solution to Reduce Spurs
8. Programmable Phase Adjustment
9. Programmable Charge Pump Current
10. Programmable Output Power Level
11. SPI or uWire (4-Wire Serial Interface)
12. Single Power Supply Operation: 3.3 V
3. Applications
1. Test and Measurement Equipment
2. Cellular Base-Station
3. Microwave Backhaul
4. High-Performance Clock Source for High-Speed Data Converters
5. Software Defined Radio
4. Pin configuration
5. Function Description
1. Input signal
The PLL requires an input signal to lock. The input signal is also used for VCO calibration, so the appropriate signal needs to be applied before starting programming. The input signal goes to the OSCinP and OSCinM pins of the device (there is an internal bias and requires an AC coupling capacitor in series before the pins). This is a differential buffer, so the total swing is the OSCinM signal minus the OSCinP signal. Differential and single-ended signals can be used. Below is an example of the maximum signal level in each mode. Proper termination and matching on both sides is important.
2. Input signal path
The input signal path contains components between the input (OSCin) buffer and the phase detector. The best PLL noise floor achieves the highest dual phase detector frequency with a 200MHz input signal. To meet a wide range of applications, the input signal path contains the following components for flexible configuration before the phase detector. Every component can be bypassed. PLL Phase Detector and Charge Pump A PLL phase detector, also known as a phase frequency detector (PFD), compares the outputs of the post-R and N-dividers and generates a correction current corresponding to the phase error with the charge pump until the two signals are in phase with each other aligned (PLL is locked). The charge pump output converts the correction current pulses to a DC voltage applied to the VCO tuning voltage (Vtune) through an external component (loop filter). The charge pump gain level is programmable, allowing the loop bandwidth of the PLL to be modified.
3. N divider and fractional circuits
The divider-by-N (12-bit) includes a multistage noise shaping (MASH) sigma-delta modulator with programmable orders from 1 to 4, which performs fractional compensation to achieve any value from 1 to (232 – 1) Fraction denominator. Using programmable registers, PLL_N is the integer part and PLL_NUM / PLL_DEN are Fractional part, so the total N divider value is determined by PLL_N + PLL_NUM / PLL_DEN. This allows the output frequency to be a fraction of the phase detector frequency. The higher the denominator, the finer the resolution steps of the output. There is an N-divider prescaler (PLL_N_PRE) between the VCO and the N-divider, which performs a division by 2 or 4. Typically 2 is chosen for higher performance in fractional mode, while 4 may be the value needed for low power operation and when N is close to its maximum value.
4. Voltage Controlled Oscillator
The Voltage Controlled Oscillator (VCO) is fully integrated. The VCO has a frequency range of 3.55 to 7.1 GHz, so it covers an octave. Channel divider allows all other lower frequencies to be generated ies. The VCOdoubler allow the generation of all other higher frequencies. The output frequency of the VCO is inverse proportional to the DC voltage present at the tuning voltage point on pin Vtune. The tuning range is 0 V to 2.5 V. 0 V generates the maximum frequency and 2.5 V generates the minimum frequency. This VCO requires a calibration procedure for each frequency selected to lock on. Each VCO calibration will force the tuning voltage to mid value and calibrate the VCO circuit. Any frequency setting in fast calibration occurs in the range of Vtune pin 0 V to 2.5 V. The VCO is designed to remained locked over the entire temperature range the device can support.
