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1. Describe
The LTC®2364-18 is a low noise, low power, high speed 18-bit successive approximation register (SAR) ADC. The LTC2364-18 operates from a 2.5V supply with 0V To VREF Pseudo-Differential Unipolar Input Range vs VREF The range is from 2.5V to 5.1V. The LTC2364-18 consumes only 3.4mW and up to ±2.5LSB INL max, no omissions The encoding is 18 bits, and the signal-to-noise ratio is 97dB. The LTC2364-18 features a high-speed SPI-compatible serial interface supporting 1.8V, 2.5V, 3.3V and 5V logic It also has a daisy-chain mode. Fast 250ksps Cycle-free throughput enables the LTC2364-18 Ideal for a variety of high-speed applications. An internal oscillator sets the conversion time, simplifying external timing considerations. LTC2364-18 Automatic power down between transitions, reducing Power consumption proportional to sample rate.
2. Feature
1. 250ksps throughput
2. ±2.5LSB INL (max)
3. Guaranteed 18 bits without missing codes
4. Low power consumption: 3.4mW at 250ksps, 3.4µW at 250sps
5. 97dB SNR (typ) at fIN = 2kHz
6. –120dB THD (typ) at fIN = 2kHz
7. Guaranteed operating temperature up to 125°C
8. 2.5V power supply
9. Pseudo-differential unipolar input range: 0V to VREF
10. VREF input range is 2.5V to 5.1V
11. No pipeline delay, no cycle delay
12. 1.8V to 5V I/O voltage
13. SPI compatible serial I/O with daisy chain mode
14. Internal conversion clock
15. 16-pin MSOP and 4mm × 3mm DFN packages
3. Application
1. medical imaging
2. High-speed data acquisition
3. Portable or compact instruments
4. Industrial process control
5. Low power battery powered meter
6. ATE
4. Pin configuration
5. Application Information
1. Overview
The LTC2364-18 is a low noise, low power, high speed 18-bit successive approximation register (SAR) ADC. Operating from a single 2.5V supply, the LTC2364-18 supports a pseudo-differential unipolar input range of 0V to VREF with a VREF range of 2.5V to 5.1V, making it ideal for high performance applications requiring a wide dynamic range. LTC2364-18 achieves ±2.5LSB INL max without Missing code at 18 bits and 97dB SNR. Fast 250ksps throughput with no cycle delay makes the LTC2364-18 ideal for a wide variety of high-speed applications. An internal oscillator sets the conversion time, simplifying external timing considerations. The LTC2364-18 dissipates only 3.4mW at 250ksps, while providing an automatic power-down feature to further reduce power dissipation during periods of inactivity.
2. Converter operation
The LTC2364-18 operates in two stages. During the acquisition phase, a charge redistribution capacitor D/A converter (CDAC) is connected to the IN+ and IN- pins to sample the pseudo-differential analog input voltage. A rising edge on the CNV pin initiates a conversion. During the conversion phase, the 18-bit CDACs are sequenced through a successive approximation algorithm, using differential comparators to effectively compare the sampled input to a binary-weighted fraction of the reference voltage (e.g. VREF/2, VREF/4…VREF/262144). At the end of the conversion , the CDAC output is close to the sampled analog input. The ADC control logic then prepares the 18-bit digital output code for serial transmission.
3. Analog input
The analog inputs of the LTC2364-18 are pseudo-differential to reduce any unwanted signals common to both inputs. The analog input can be modeled by the equivalent circuit shown in Figure 3. Diodes at the input provide ESD protection. During the acquisition phase, each input sees approximately 45pF (CIN) from the sampling CDAC in series with 40Ω (RON) from the on-resistance of the sampling switch. The IN+ input generates a current spike when charging the CIN capacitor during acquisition. During the conversion process, the analog input draws only a small leakage current.
4. Input drive circuit
A low impedance source can directly drive the high impedance input of the LTC2364-18 without gain error. High impedance sources should be buffered to minimize settling time during acquisition and optimize ADC distortion performance. Minimizing settling time is important, even for DC inputs, because the ADC input can generate current spikes as it enters the acquisition. For best performance, a buffer amplifier should be used to drive the analog input of the LTC2364-18. The amplifier provides low output impedance for fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the current spikes drawn by the ADC input.
5. Input filtering
The noise and distortion of the buffer amplifier and signal source must be considered as they add to the ADC noise and distortion. A noisy input signal should be filtered with an appropriate filter before the buffer amplifier input to minimize noise. Another filter network consisting of LPF2 should be used between the buffer and the ADC input to minimize the noise contribution of the buffer and help minimize the distance The city from the sampled transient reflections into the buffer. A long RC time constant at the analog input slows down the settling speed of the analog input. Therefore, LPF2 requires a wider bandwidth than LPF1. A buffer amplifier with low noise density must be selected to minimize SNR degradation. High quality capacitors and resistors should be used in RC filters as these components add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can deform due to self-heating and damage that can occur during soldering. Metal film surface-mount resistors are much less affected by these two issues.
6. Pseudo-differential unipolar input
For most applications, we recommend the low power LT6202 ADC driver to drive the LTC2364-18. With a low noise density of 1.9nV/√Hz and low supply current of 3mA, the LT6202 is flexible and can be configured to convert signals of various amplitudes to the LTC2364-18's 0V to 5V input range. The LT6202 can also be used to buffer and convert large true bipolar signals that swing below ground to the 0V to 5V input range of the LTC2364-18. In this case, the LT6202 is configured as an inverting amplifier stage whose role is to attenuate and level shift the input signal to the 0V to 5V input range of the LTC2364-18. In an inverting configuration, the single-ended input signal source no longer drives the high impedance input directly. The input impedance is set by resistor RIN. RIN must be carefully selected based on the source impedance of the signal source. Higher RIN values tend to reduce the noise and distortion of the LT6202 and LTC2364-18 as a system.
