• Manufacturer Part# MC74HCT373AN
  • Product CategoryIntegrated Circuits (ICs)
  • Short DescriptionIC LATCH TRNSP OCTAL 3ST 20DIPD-Type Transparent L...
  • More DetailN/A
In Stock: 3457

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Technical Details

  • Series:74HCT
  • Packaging:Tube 
  • Part Status:Obsolete
  • Logic Type:D-Type Transparent Latch
  • Circuit:8:8
  • Output Type:Tri-State
  • Voltage - Supply:4.5 V ~ 5.5 V
  • Independent Circuits:1

 

  • Delay Time - Propagation:28ns
  • Current - Output High, Low:6mA, 6mA
  • Operating Temperature:-55°C ~ 125°C
  • Mounting Type:Through Hole
  • Package / Case:20-DIP (0.300", 7.62mm)
  • Supplier Device Package:20-PDIP
  • Base Part Number:74HCT373

Description

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   brenda@hongda-ic.com


1. Describe

MC74HCT373AN can be used as a level converter Connect TTL or NMOS output to high-speed CMOS input. The pin arrangement of HCT373A is the same as that of LS373. The eight latches of HCT373A are transparent D-type latches. When Latch Enable is high, the Q output follows the data input. When Latch Enable is pulled low, it meets the established and maintained data Time became locked. The output enable does not affect the state of the latch, but when Output enable is high, all outputs are forced to high impedance state. Therefore, even if the output is not, the data may be latched Enable. HCT373A is functionally the same as HCT573A, which has The input pins and output pins on the other side of the package. The device is functionally similar to HCT533A, which has Inverted output.

2. Features

    1. Output Drive Capability: 15 LSTTL Loads

    2. TTL/NMOS−Compatible Input Levels

    3. Outputs Directly Interface to CMOS, NMOS, and TTL

    4. Operating Voltage Range: 4.5 to 5.5 V

    5. Low Input Current: 1.0 A

    6. In Compliance with the Requirements Defined by JEDEC Standard No. 7 A

    7. Chip Complexity: 196 FETs or 49 Equivalent Gates

    8. These Devices are Pb−Free and are RoHS Compliant

3. PIN ASSIGNMENT

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4. PACKAGE DIMENSIONS

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