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1. Description
This 8-bit input/output (I/O) expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 6-V VCC operation. The PCF8574A device provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with highcurrent drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to VCC is active.
2. Features
1. Low standby-current consumption of 10 μA max
2. I2C to parallel-port expander
3. Open-drain interrupt output
4. Compatible with most microcontrollers
5. Latched outputs with high-current drive capability for directly driving LEDs
6. Latch-up performance exceeds 100 mA Per JESD 78, Class II
3. Applications
1. Telecom shelters: filter units
2. Servers
3. Routers (telecom switching equipment)
4. Personal computers
5. Personal electronics
6. Industrial automation
7. Products with GPIO-Limited Processors
4. Pin Configuration
5. Pin Functions
6. Feature Description
I2C communication with this device is initiated by a commander sending a start condition, a high-to-low transition on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, mostsignificant bit (MSB) first, including the data direction bit (R/ W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the responder device must not be changed between the start and the stop conditions. The data byte follows the address acknowledge. If the R/ W bit is high, the data from this device are the values read from the P port. If the R/ W bit is low, the data are from the commander, to be output to the P port. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the commander, following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the clock cycle for the acknowledge. A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the commander.
