XC6SLX25-2CSG324I

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1. Feature summary

    1. Spartan-6 Family:

        - Spartan-6 LX FPGA: Logic optimized

        - Spartan-6 LXT FPGA: High-speed serial connectivity

    2. Designed for low cost

        - Multiple efficient integrated blocks

        - Optimized selection of I/O standards

        - Staggered pads

        - High-volume plastic wire-bonded packages

    3. Low static and dynamic power

        - 45 nm process optimized for cost and low power

        - Hibernate power-down mode for zero power

        - Suspend mode maintains state and configuration with multi-pin wake-up, control enhancement

        - Lower-power 1.0V core voltage (LX FPGAs, -1L only)

        - High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)

    4. Multi-voltage, multi-standard SelectIO™ interface banks

        - Up to 1,080 Mb/s data transfer rate per differential I/O

        - Selectable output drive, up to 24 mA per pin

        - 3.3V to 1.2V I/O standards and protocols

        - Low-cost HSTL and SSTL memory interfaces

        - Hot swap compliance

        - Adjustable I/O slew rates to improve signal integrity

    5. High-speed GTP serial transceivers in the LXT FPGAs

        - Up to 3.2 Gb/s

        - High-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI

    6. Integrated Endpoint block for PCI Express designs (LXT)

    7. Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.

    8. Efficient DSP48A1 slices

        - High-performance arithmetic and signal processing

        - Fast 18 x 18 multiplier and 48-bit accumulator

        - Pipelining and cascading capability

        - Pre-adder to assist filter applications

    9. Integrated Memory Controller blocks

        - DDR, DDR2, DDR3, and LPDDR support

        - Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)

        - Multi-port bus structure with independent FIFO to reduce design timing issues

  10. Abundant logic resources with increased logic capacity

        - Optional shift register or distributed RAM support

        - Efficient 6-input LUTs improve performance and minimize power

        - LUT with dual flip-flops for pipeline centric applications

  11. Block RAM with a wide range of granularity

        - Fast block RAM with byte write enable

        - 18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs

  12. Clock Management Tile (CMT) for enhanced performance

        - Low noise, flexible clocking

        - Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion

        - Phase-Locked Loops (PLLs) for low-jitter clocking

        - Frequency synthesis with simultaneous multiplication, division, and phase shifting

        - Sixteen low-skew global clock networks

 13. Simplified configuration, supports low-cost standards

       - 2-pin auto-detect configuration

       - Broad third-party SPI (up to x4) and NOR flash support

       - Feature rich Xilinx Platform Flash with JTAG

       - MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection

  14. Enhanced security for design protection

        - Unique Device DNA identifier for design authentication

        - AES bitstream encryption in the larger devices

  15. Faster embedded processing with enhanced, low cost, MicroBlaze™ soft processor

  16. Industry-leading IP and reference designs

2. Input/Output

The number of I/O pins varies from 102 to 576, depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 3.3V. The Spartan-6 FPGA SelectIO Resources User Guide describes the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins, all other package pins have the same I/O capabilities, constrained only by certain banking rules. All user I/O is bidirectional; there are no input-only pins. All I/O pins are organized in banks, with four banks on the smaller devices and six banks on the larger devices. Each bank has several common VCCO output supply-voltage pins, which also powers certain input buffers. Some single-ended input buffers require an externally applied reference voltage (VREF). There are several dual-purpose VREF-I/O pins in each bank. In a given bank, when I/O standard calls for a VREF voltage, each VREF pin in that bank must be connected to the same voltage rail and can not be used as an I/O pin.

3. Description

The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.

4. I/O Electrical Characteristics

Single-ended outputs use a conventional CMOS push/pull output structure, driving High towards VCCO or Low towards ground, and can be put into high-Z state. Many I/O features are available to the system designer to optionally invoke in each I/O in their design, such as weak internal pull-up and pull-down resistors, strong internal split-termination input resistors, adjustable output drive-strengths and slew-rates, and differential termination resistors. See the Spartan-6 FPGA SelectIO Resources User Guide for more details on available options for each I/O standard.

5. PLL

The PLL can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks in conjunction with the DCMs. The heart of the PLL is a voltage-controlled oscillator (VCO) with a frequency range of 400 MHz to 1,080 MHz, thus spanning more than one octave. Three sets of programmable frequency dividers (D, M, and O) adapt the VCO to the required application. The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL phase comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the VCO within its controllable frequency range. The VCO has eight equally spaced outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the six output dividers, O0 to O5 (each programmable by configuration to divide by any integer from 1 to 128).

6. CLBs, Slices, and LUTs

Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical columns. There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinat orial and sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. Expert designers can also instantiate them.