XC6SLX9-2TQG144I

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1. Spartan-6 FPGA Features Summary

    1. Spartan-6 Family

        - Spartan-6 LX FPGA: Logic optimized

        - Spartan-6 LXT FPGA: High-speed serial connectivity

    2. Designed for low cost

        - Multiple efficient integrated blocks

        - Optimized selection of I/O standards

        - Staggered pads

        - High-volume plastic wire-bonded packages

    3. Low static and dynamic power

        - 45 nm process optimized for cost and low power

        - Hibernate power-down mode for zero power

        - Suspend mode maintains state and configuration with multi-pin wake-up, control enhancement

        - Lower-power 1.0V core voltage (LX FPGAs, -1L only)

        - High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)

    4. Multi-voltage, multi-standard SelectIO™ interface banks

        - Up to 1,080 Mb/s data transfer rate per differential I/O

        - Selectable output drive, up to 24 mA per pin

        - 3.3V to 1.2V I/O standards and protocols

        - Low-cost HSTL and SSTL memory interfaces

        - Hot swap compliance

        - Adjustable I/O slew rates to improve signal integrity

    5. High-speed GTP serial transceivers in the LXT FPGAs

        - Up to 3.2 Gb/s

        - High-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI

    6. Integrated Endpoint block for PCI Express designs (LXT)

    7. Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.

    8. Efficient DSP48A1 slices

        - High-performance arithmetic and signal processing

        - Fast 18 x 18 multiplier and 48-bit accumulator

        - Pipelining and cascading capability

        - Pre-adder to assist filter applications

    9. Integrated Memory Controller blocks

        - DDR, DDR2, DDR3, and LPDDR support

        - Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth) 

        - Multi-port bus structure with independent FIFO to reduce design timing issues

  10. Abundant logic resources with increased logic capacity

       - Optional shift register or distributed RAM support

       - Efficient 6-input LUTs improve performance and minimize power

       - LUT with dual flip-flops for pipeline centric applications

  11. Block RAM with a wide range of granularity

       - Fast block RAM with byte write enable

       - 18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs

  12. Clock Management Tile (CMT) for enhanced performance

       - Low noise, flexible clocking

       - Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion

       - Phase-Locked Loops (PLLs) for low-jitter clocking

       - Frequency synthesis with simultaneous multiplication, division, and phase shifting

       - Sixteen low-skew global clock networks

  13. Simplified configuration, supports low-cost standards

        - 2-pin auto-detect configuration

        - Broad third-party SPI (up to x4) and NOR flash support

        - Feature rich Xilinx Platform Flash with JTAG

        - MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection

  14. Enhanced security for design protection

        - Unique Device DNA identifier for design authentication

        - AES bitstream encryption in the larger devices

  15. Faster embedded processing with enhanced, low cost, MicroBlaze™ s Regular processor

  16. Industry-leading IP and reference designs feature

2. Description

The Spartan®-6 series provides leading system integration functions for high-volume applications at the lowest total cost. this The 13-member series provides an expanded density from 3,840 logic units to 147,443 logic units, and the power consumption is only half of the previous The Spartan family, and faster and more comprehensive connections. Based on the mature 45nm low-power copper process technology, The Spartan-6 series provides the best balance of cost, power consumption and performance, providing a new and more efficient dual-register 6-input look-up table (LUT) logic and a wealth of built-in system-level module options. Including 18 Kb (2 x 9 Kb) RAM blocks, second generation DSP48A1 slice, SDRAM memory controller, enhanced mixed-mode clock management module, SelectIO™ technology, power optimized high-speed serial transceiver module, PCI Express® compatible endpoint module, advanced system-level power management Automatic detection of modes, configuration options, and enhanced IP security through AES and Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGA provides the best solution High-capacity logic design, consumer-oriented DSP design and cost-sensitive embedded applications. Spartan-6 FPGA Yes The programmable silicon foundation of the target design platform provides integrated software and hardware components to achieve Designers focus on innovation at the beginning of the development cycle.

3. Configuration

Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits is between 3 Mb and 33 Mb depending on device size and user-design implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available. Bit-serial configurations can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal, or slave serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurations, master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal for the 8- and 16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an external clock, which can be faster or more precise than the internal clock. The available JTAG pins use boundary-scan protocols to load bit-serial configuration data. The bitstream configuration information is generated by the ISE® software using a program called BitGen. Configuration The process usually executes the following sequence:

1. Detect power-on (power-on reset) or PROGRAM_B at low level.

2. Clear the entire configuration memory.

3. The sampling mode pin determines the configuration mode: master or slave, bit serial or parallel.

4. Load the configuration data from the bus width detection mode, followed by the synchronization word, check It is used for the correct device code and ends with a cyclic redundancy check (CRC) of the complete bitstream.

5. Start a user-defined sequence of events: release the internal reset (or preset) of the trigger, choose to wait The DCM and/or PLL lock, activate the output driver, and switch the DONE pin to a high level.

Master Serial Peripheral Interface (SPI) and Master Byte-wide Peripheral Interface (BPI) are two commonly used methods Used to configure the FPGA. The Spartan-6 FPGA configures itself via a direct-connected industry standard SPI serial Flash PROM. When Spartan-6 FPGA is connected to industry standard parallel NOR flash memory, it can configure itself through BPI. Please note that XC6SLX4, XC6SLX25 and XC6SLX25T do not support BPI configuration, use Spartan-6 FPGA in TQG144 and CPG196 packages. Spartan-6 FPGA supports MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in one Single configuration source. The FPGA application controls which configuration is loaded next and when it is loaded. The Spartan-6 FPGA also includes a unique, factory-programmed Device DNA identifier, which can be used for tracking purposes, anti-clone design, or IP protection. In the largest devices, the bitstream can be copy protected using AES encryption.

4. I/O Electrical Characteristics

Single-ended outputs use a conventional CMOS push/pull output structure, driving High towards VCCO or Low towards ground, and can be put into high-Z state. Many I/O features are available to the system designer to optionally invoke in each I/O in their design, such as weak internal pull-up and pull-down resistors, strong internal split-termination input resistors, adjustable output drive-strengths and slew-rates, and differential termination resistors. See the Spartan-6 FPGA SelectIO Resources User Guide for more details on available options for each I/O standard.

5. Integrated endpoint module for PCI Express design

The PCI Express standard is a point-to-point serial interface standard based on data packets. Differential signal transmission The use of an embedded clock eliminates the clock-to-data deviation problem of the traditional wide parallel bus. PCI Express Basic Specification 1.1 defines a bit rate of 2.5 Gb/s for each channel and each direction (transmit and receive). when Use 8B/10B encoding, which supports a data rate of 2.0 Gb/s per channel. The Spartan-6 LXT device includes an integrated endpoint module for PCI Express technology that complies with PCI The module can be highly configured according to the system design requirements and serves as a compatible single-channel endpoint. The integrated endpoint module is connected to the GTP transceiver for serialization/deserialization and to block RAM for data buffering. Together, these elements implement the physical layer, the data link layer, and the transaction layer of the protocol. Xilinx provides a lightweight (<200 LUT), configurable, and easy-to-use LogiCORE™ IP that combines various building blocks (integrated endpoint blocks of PCI Express technology, GTP transceivers, block RAM and clock resources) into a compliant Endpoint solutions. The system designer can control many configurable parameters: maximum payload size, reference clock frequency, and base address register decoding and filtering.