XC7K480T-2FFG1156I

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1. Description

Xilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include:

  1. Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factor packaging for smallest PCB footprint.

  2. Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitive applications.

  3. Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.

  4. Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology.

Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.

2. Summary of 7 Series FPGA Features

    1. Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.

    2. 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.

    3. High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.

    4. High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.

    5. A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.

    6. DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.

    7. Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.

    8. Quickly deploy embedded processing with MicroBlaze™ processor.

    9. Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.

  10. Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.

  11. Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.

  12. Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.

3. Mixed-Mode Clock Manager and Phase-Locked Loop

The MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD). There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL, O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128. The MMCM and PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but not the best jitter attenuation. Optimized mode allows the tools to find the best setting.

4. XADC (Analog to Digital Converter)

Highlights of the XADC architecture include:

    1. Dual 12-bit 1 MSPS analog-to-digital converter (ADC)

    2. Up to 17 flexible and user-configurable analog inputs

    3. On-chip or external reference options

    4. On-chip temperature (±4°C maximum error) and power supply (±1% maximum error) sensors

    5. Continuous JTAG access to ADC measurements

All Xilinx 7 series FPGAs (except XC7S6 and XC7S15) integrate a new flexible analog interface called XADC. when Combined with the programmable logic functions of the 7 series FPGAs, XADC can handle a wide range of data Acquisition and monitoring requirements. XADC contains two 12-bit 1 MSPS ADCs with independent track and hold amplifiers, an on-chip analog multiplexer (up to Supports 17 external analog input channels), as well as on chip thermal sensors and power sensors. These two ADCs can be configured as Simultaneously sample two external input analog channels. Track and hold amplifier supports a range of analog inputs Signal types, including unipolar, bipolar, and differential. The analog input can at least support the signal bandwidth 500 KHz, sampling rate is 1MSPS. An external analog multiplexer can be used to support a higher analog bandwidth mode with a dedicated analog input. XADC can choose to use on-chip reference circuit (±1%), which eliminates the need for any external active Components used for basic on-chip monitoring of temperature and power rails. In order to achieve a complete 12-bit performance ADC, it is recommended to use an external 1.25V reference IC. If XADC is not instantiated in the design, it will digitize the output of all on-chip sensors by default. The most recent measurement results (along with the maximum and minimum readings) are stored in dedicated registers for access at any time through the JTAG interface. User-defined alarm thresholds can automatically indicate over-temperature events and unacceptable power changes. The user-specified limit (for example, 100°C) can be used to initiate automatic power-down.