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1. Description
The XC9572-15PC84I is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview
2. Features
1. 7.5 ns pin-to-pin logic delays on all pins
2. fCNT to 125 MHz
3. 72 macrocells with 1,600 usable gates
4. Up to 72 user I/O pins
5. 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
6. Enhanced pin-locking architecture
7. Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
8. Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
9. Programmable power reduction mode in each macrocell
10. Slew rate control on individual outputs
11. User programmable ground pin capability
12. Extended pattern security features for design protection
13. High-drive 24 mA outputs
14. 3.3V or 5V I/O capability
15. Advanced CMOS 5V FastFLASH™ technology
16. Supports parallel programming of more than one XC9500 concurrently
17. Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages
3. Product appearance overview
