• Manufacturer Part# XC9572XL-10VQG44C
  • Product CategoryIntegrated Circuits (ICs)
  • Short DescriptionIC CPLD 72MC 10NS 44VQFP
  • More DetailN/A
In Stock: 30233

Can ship immediately

Technical Details

  • Series:XC9500XL
  • Packaging:Tray 
  • Part Status:Active
  • Programmable Type:In System Programmable (min 10K program/erase cycles)
  • Delay Time tpd(1) Max:10.0ns
  • Voltage Supply - Internal:3 V ~ 3.6 V
  • Number of Logic Elements/Blocks:4
  • Number of Macrocells:72

 

  • Number of Gates:1600
  • Number of I/O:34
  • Operating Temperature:0°C ~ 70°C (TA)
  • Mounting Type:Surface Mount
  • Package / Case:44-TQFP
  • Supplier Device Package:44-VQFP (10x10)
  • Base Part Number:XC9572XL

Description

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   brenda@hongda-ic.com


1. Describe

The XC9572XL is a 3.3V CPLD for high performance, low voltage applications in leading edge communications and computing systems. It consists of four 54V18 function blocks, providing 1,600 usable gates with a propagation delay of 5 ns.

2. Features

    1. 5 ns pin-to-pin logic delays

    2. System frequency up to 178 MHz

    3. 72 macrocells with 1,600 usable gates

    4. Available in small footprint packages

        - 44-pin PLCC (34 user I/O pins)

        - 44-pin VQFP (34 user I/O pins)

        - 48-pin CSP (38 user I/O pins)

        - 64-pin VQFP (52 user I/O pins)

        - 100-pin TQFP (72 user I/O pins)

        - Pb-free available for all packages

    5. Optimized for high-performance 3.3V systems

        - Low power operation

        - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals

        - 3.3V or 2.5V output capability

        - Advanced 0.35 micron feature size CMOS Fast FLASH™ technology

    6. Advanced system features

        - In-system programmable

        - Superior pin-locking and routability with Fast CONNECT™ II switch matrix

        - Extra wide 54-input Function Blocks

        - Up to 90 product-terms per macrocell with individual product-term allocation

        - Local clock inversion with three global and one product-term clocks

        - Individual output enable per output pin

        - Input hysteresis on all user and boundary-scan pin inputs

        - Bus-hold circuitry on all user pin inputs

        - Full IEEE Standard 1149.1 boundary-scan (JTAG)

    7. Fast concurrent programming

    8. Slew rate control on individual outputs

    9. Enhanced data security features

  10. Excellent quality and reliability

        - Endurance exceeding 10,000 program/erase cycles

        - 20 year data retention

        - ESD protection exceeding 2,000V

  11. Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package


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