82P2281PFG

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1. FEATURES

    1. The device can be configured as T1, E1 or J1

    2. Supports T1/E1/J1 long haul/short haul line interface

    3. HPS for 1+1 protection without external relays

    4. Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024 Hz

    5. Selectable internal line termination impedance: 100 Ω (for T1), 75 Ω / 120 Ω (for E1) and 110 Ω (for J1)

    6. Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encoding/decoding

    7. Provides T1/E1/J1 short haul pulse templates, long haul LBO (per ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and userprogrammable arbitrary pulse template

    8. Supports T1.102 line monitor

    9. Transmit line short-circuit detection and protection

  10. Separate Transmit and Receive Jitter Attenuators (2 per link)

  11. Indicates the interval between the write pointer and the read pointer of the FIFO in JA

  12. Loss of signal indication with programmable thresholds according to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1)

  13. Supports Analog Loopback, Digital Loopback and Remote Loopback

  14. The receiver and transmitter can be individually powered down

  15. The device can be configured as T1, E1 or J1

  16. Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY000278, TR-TSY-000008), E1 (per ITU-T G.704), J1 (per JT G.704) and un-framed mode

  17. Supports T1/J1 Super Frame and Extended Super Frame, T1 Digital Multiplexer and Switch Line Carrier - 96, E1 CRC Multi-frame and Signaling Multi-frame

  18. Signaling extraction/insertion for CAS and RBS signaling

  19. Provides programmable system interface supporting MitelTM STbus, AT&TTM CHI and MVIP bus, 8.192 Mb/s multiplexed bus and 1.544 Mb/s or 2.048 Mb/s non-multiplexed bus

  20. Three HDLC controllers with separate 128-byte transmit and receive FIFOs per controller

  21. Programmable bit insertion and bit inversion on per channel/ timeslot basis

  22. Provides Bit Oriented Message (BOM) generation and detection

  23. Provides Automatic Performance Report Message (APRM) generation

  24. Detects and generates alarms (AIS, RAI)

  25. Provides performance monitor to count Bipolar Violation error, Excess Zero error, CRC error, framing bit error, far end CRC error, out of frame and change of framing alignment position

  26. Supports System Loopback, Payload Loopback, Digital Loopback and Inband Loopback

  27. Detects and generates selectable PRBS and QRSS

  28. Transmission and Extraction of Synchronization Supply Message (SSM) in BITS application

2. CONTROL INTERFACE

    1. Supports Serial Peripheral Interface (SPI) microprocessor and parallel Intel/Motorola non-multiplexed microprocessor interface

    2. Global hardware and software reset

    3. One general purpose I/O pin

    4. Device power down

3. APPLICATIONS

    1. C.O, PABX, ISDN PRI

    2. Wireless Base Stations

    3. T1/E1/J1 ATM Gateways, Multiplexer

    4. T1/E1/J1 Access Networks

    5. LAN/WAN Router

    6. Digital Cross Connect

    7. SONET/SDH Add/Drop Equipment

    8. Clock recovery at 1.544 MHz / 2.048 MHz for BITS application with SSM support

    9. If you are using a bits application, please refer to AN-1029

4. Pin configuration