C8051F130-GQ

1. Description

The C8051F12x and C8051F13x device families are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (100-pin TQFP) or 32 digital I/O pins (64-pin TQFP).

Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.

2. Features

     1. High-Speed pipelined 8051-compatible CIP-51 microcontroller core (100 MIPS or 50 MIPS)

     2. In-system, full-speed, non-intrusive debug interface (on-chip)

     3. True 12 or 10-bit 100 ksps ADC with PGA and 8-channel analog multiplexer

     4. True 8-bit 500 ksps ADC with PGA and 8-channel analog multiplexer (C8051F12x Family)

     5. Two 12-bit DACs with programmable update scheduling (C8051F12x Family)

     6. 2-cycle 16 by 16 Multiply and Accumulate Engine (C8051F120/1/2/3 and C8051F130/1/2/3)

     7. 128 or 64 kB of in-system programmable Flash memory

     8. 8448 (8 k + 256) bytes of on-chip RAM

     9. External Data Memory Interface with 64 kB address space

   10. SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware

   11. Five general purpose 16-bit Timers

   12. Programmable Counter/Timer Array with 6 capture/compare modules

   13. On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor

3. Analog Peripherals

   - 10 or 12-bit SAR ADC

       • ± 1 LSB INL • Programmable throughput up to 100 ksps

       • Up to 8 external inputs; programmable as singleended or differential • Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5

       • Data-dependent windowed interrupt generator

       • Built-in temperature sensor

   - 8-bit SAR ADC (‘F12x Only)

       • Programmable throughput up to 500 ksps • 8 external inputs (single-ended or differential)

       • Programmable amplifier gain: 4, 2, 1, 0.5

   - Two 12-bit DACs (‘F12x Only)

       • Can synchronize outputs to timers for jitter-free waveform generation

   - Two Analog Comparators

   - Voltage Reference

   - VDD Monitor/Brown-Out Detector

4. On-Chip JTAG Debug & Boundary Scan

   - On-chip debug circuitry facilitates full-speed, nonintrusive in-circuit/in-system debugging

   - Provides breakpoints, single-stepping, watchpoints,stack monitor; inspect/modify memory and registers

   - Superior performance to emulation systems using ICE-chips, target pods, and sockets

   - IEEE1149.1 compliant boundary scan

   - Complete development kit 100-Pin TQFP or 64-Pin TQFP Packaging

   - Temperature Range: –40 to +85 °C

   - RoHS Available

5. High Speed 8051 µC Core

   - Pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks

   - 100 MIPS or 50 MIPS throughput with on-chip PLL

   - 2-cycle 16 x 16 MAC engine (C8051F120/1/2/3 and C8051F130/1/2/3 only)

6. Memory

   - 8448 bytes internal data RAM (8 k + 256)

   - 128 or 64 kB Banked Flash; in-system programmable in 1024-byte sectors

   - External 64 kB data memory interface (programmable multiplexed or non-multiplexed modes)

7. Digital Peripherals

   - 8 byte-wide port I/O (100TQFP); 5 V tolerant

   - 4 Byte-wide port I/O (64TQFP); 5 V tolerant

   - Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial ports available concurrently

   - Programmable 16-bit counter/timer array with 6 capture/compare modules

   - 5 general purpose 16-bit counter/timers

   - Dedicated watchdog timer; bi-directional reset pin 

8. Clock Sources

   - Internal precision oscillator: 24.5 MHz

   - Flexible PLL technology

   - External Oscillator: Crystal, RC, C, or clock

9. Voltage Supples

   - Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)

   - Power saving sleep and shutdown modes