GD32F103RET6

description

The GD32F103RET6 device is a 32-bit general-purpose microcontroller based on ARM®Cortex™-M3 RISCcore, which has the best ratio in terms of processing power, reduced power consumption and peripheral devices. Cortex™-M3 is the next generation processor core, tightly integrated with the Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debugging support. The GD32F103RET6 device integrates an ARM®Cortex™-M3 32-bit processor core with a working frequency of 108MHz and zero flash memory access rights. Wait state for maximum efficiency. It provides up to 3 MB of on-chip flash memory and up to 96KB of SRAM memory. Various enhanced I/O and peripheral devices are connected to the two APB buses. The device provides up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose 16-bit timers, two basic timers and two PWM advanced timers, as well as standard and advanced communication interfaces: multiple One Up to three SPI, two I2C, three USART, two UART, two I2S, USBD, CAN and aSDIO. The device uses a 2.6 to 3.6 V power supply and has an operating temperature range of –40 to +85°C. Several power saving modes provide the flexibility to achieve maximum optimization between wake-up delay and power consumption, which is especially important in low-power applications.

Feature

1. ARM®Cortex™-M3 core

The Cortex™-M3 processor is the latest generation of ARM® processors for embedded systems. It was developed to provide a low-cost platform that can meet the needs of MCU implementation, reduce the number of pins and reduce power consumption, while providing excellent computing performance and advanced system response to interrupts.

   1. 32-bit ARM®Cortex™-M3 processor core

    2. Up to 108MHz operating frequency

   3. Single cycle multiplication and hardware divider

   4. Integrated Nested Vectored Interrupt Controller (NVIC)

   5. 24-bit SysTick timer

The Cortex™-M3 processor is based on the ARMv7 architecture and supports Thumb and Thumb-2 instruction sets. Cortex™-M3 also provides some of the following system peripherals:

   1. The internal bus matrix is connected with I code bus, D code bus, system bus, dedicated peripheral bus (PPB) and debugging access.

   2. Nested vectored interrupt controller (NVIC).

   3. Flash patches and breakpoints (FPB).

   4. Data observation point and tracking (DWT).

   5. Instrument tracking macro unit (ITM).

   6. Embedded tracking macrocell (ETM).

   7. Serial JTAG debug port (SWJ-DP).

   8. Trace Port Interface Unit (TPIU).

   9. Memory protection unit (MPU).

2. On-chip memory

   1. Up to 3072 KB of flash memory

   2. SRAM up to 96Kb

The ARM®Cortex™-M3 processor adopts the Harvard architecture and can use a separate bus to fetch instructions and load/store data. Up to 3072 KB of internal Flash and 96 KB of internal SRAM can be used to store programs and data, both of which can be accessed (R/W)