MC56F8037VLH

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1. Describe

MC56F8037VLH are members of the Digital Signal Controller (DSC) series based on the 56800E core. It combines the processing power of DSP and the functions of a microcontroller on a single chip Use a flexible set of peripherals to create a very cost-effective solution. Due to its low cost, configuration flexibility and compact program code, 56F8037/56F8027 is very suitable for many applications. 56F8037/56F8027 includes many peripherals that are particularly useful for industrial control, motion control, household appliances, general inverters, smart sensors, fire protection and safety System, switch mode power supply, power management and medical monitoring applications. The 56800E core is based on a dual Harvard architecture composed of three execution units for parallel operation, allowing up to six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow direct generation of efficient and compact DSP and control code. This instruction set is also very efficient for C compilers, and can quickly develop optimized control applications. 56F8037/56F8027 support program execution from internal memory. Each instruction cycle can access two data operands from the on-chip data RAM. The 56F8037/56F8027 also provide up to 53 general-purpose input/output (GPIO) lines, depending on the peripheral configuration. The 56F8037 digital signal controller includes 64KB of program flash memory and 8KB of unified data/program RAM. The 56F8027 digital signal controller includes 32KB of program flash memory and 4KB of unified data/program RAM. The program flash memory can be individually erased in bulk or by page. The program flash page erase size is 512 bytes (256 words). A complete set of programmable peripherals-PWM, ADC, QSCI, QSPI, I2C, PIT, quad timers, DAC and analog comparators-supports various applications. Each peripheral can be turned off independently to save power. Any pins in these peripherals can also be used as general-purpose input/output (GPIO).

2. Features

    1. Up to 32 MIPS at 32MHz core frequency

    2. DSP and MCU functions in a unified C high-efficiency architecture

    3. 56F8037 provides 64KB (32K x 16) program flash memory

    4. 56F8027 provides 32KB (16K x 16) program flash memory

    5. 56F8037 provides 8KB (4K x 16) unified data/program RAM

    6. 56F8027 provides 4KB (2K x 16) unified data/program RAM

    7. 1 6-channel PWM module

    8. Two 8-channel 12-bit analog-to-digital converters (ADC)

    9. Two 12-bit digital-to-analog converters (DAC)

  10. Two analog comparators

  11. Three programmable interval timers (PIT)

  12. Two queued serial communication interfaces (QSCI) With LIN slave function

  13. Two queued serial peripheral interfaces (QSPI)

  14. Freescale's Scalable Controller Area Network (MSCAN) 2.0 A/B module

  15. Two 16-bit quad timers

  16. An inter-integrated circuit (I2C) Port

  17. Computer normal operation (COP)/watchdog

  18. On-chip relaxation oscillator

  19. Integrated power-on reset (POR) and low voltage Interrupt (LVI) module

  20. JTAG/enhanced on-chip emulation (OnCE™) for Unobtrusive real-time debugging

3. Digital Signal Controller Core

    1. Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

    2. As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

    3. Single-cycle 16  16-bit parallel Multiplier-Accumulator (MAC)

    4. Four 36-bit accumulators, including extension bits

    5. 32-bit arithmetic and logic multi-bit shifter

    6. Parallel instruction set with unique DSP addressing modes

    7. Hardware DO and REP loops

    8. Three internal address buses

    9. Four internal data buses

  10. Instruction set supports both DSP and controller functions

  11. Controller-style addressing modes and instructions for compact code

  12. Efficient C compiler and local variable support

  13. Software subroutine and interrupt stack with depth limited only by memory

  14. JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging

4. Peripheral Circuits

    1. One multi-function six-output Pulse Width Modulator (PWM) module

        — Up to 96MHz PWM operating clock

        — 15 bits of resolution

        — Center-aligned and Edge-aligned PWM signal mode

        — Four programmable fault inputs with programmable digital filter

        — Double-buffered PWM registers

        — Each complementary PWM signal pair allows selection of a PWM supply source from:

             – PWM generator

             – External GPIO

             – Internal timers

             – Analog comparator outputs

             – ADC conversion result which compares with values of ADC high- and low-limit registers to set PWM output

    2. Two independent 12-bit Analog-to-Digital Converters (ADCs)

        — 2 x 8 channel inputs

        — Supports both simultaneous and sequential conversions

        — ADC conversions can be synchronized by both PWM and timer modules

        — Sampling rate up to 2.67MSPS

        — 16-word result buffer registers

    3. Two 12-bit Digital-to-Analog Converters (DACs)

        — 2 microsecond settling time when output swing from rail to rail

        — Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and range

    4. Two 16-bit multi-purpose Quad Timer modules (TMRs)

        — Up to 96MHz operating clock

        — Eight independent 16-bit counter/timers with cascading capability

        — Each timer has capture and compare capability

        — Up to 12 operating modes

    5. Two Queued Serial Communication Interfaces (QSCIs) with LIN Slave functionality

        — Full-duplex or single-wire operation

        — Two receiver wake-up methods:

             – Idle line

             – Address mark

        — Four-bytes-deep FIFOs are available on both transmitter and receiver

    6. Two Queued Serial Peripheral Interfaces (QSPIs)

        — Full-duplex operation 

        — Master and slave modes

        — Four-words-deep FIFOs available on both transmitter and receiver

        — Programmable Length Transactions (2 to 16 bits)

    7. One Inter-Integrated Circuit (I2C) port

        — Operates up to 400kbps

        — Supports both master and slave operation

        — Supports both 10-bit address mode and broadcasting mode

    8. One Freescale scalable controller area network (MSCAN) module

        — Fully compliant with CAN protocol - Version 2.0 A/B

        — Support standard and extended data frames

        — Supports data rates up to 1Mbps

        — Five receiving buffers and three sending buffers

    9. Three 16-bit programmable interval timers (PIT)

  10. Two analog comparators (CMP)

        — Selectable input sources include external pins, DAC

        — Programmable output polarity

        — Output can drive timer input, PWM fault input, PWM source, external pin output and trigger ADC

             - Output falling edge and rising edge detection can generate interrupt

  11. The computer is operating normally (COP)/watchdog timer capable of selecting different clock sources

  12. Up to 53 general purpose I/O (GPIO) pins with 5V tolerance

  13. Integrated power-on reset and low-voltage interrupt module

  14. Phase-locked loop (PLL) provides high-speed clock for core and peripherals

  15. Clock source:

        — On-chip relaxation oscillator

        — External clock: crystal oscillator, ceramic resonator and external clock source

  16. JTAG/EOnCE debugging programming interface for real-time debugging