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1. Describe
The MSP430™ Ultra Low Power (ULP) FRAM platform combines a unique embedded FRAM and overall ultra low power system architecture, enabling innovators to increase performance with a lower energy budget. FRAM technology combines the speed, flexibility and endurance of SRAM with the stability and reliability of flash memory at a fraction of the cost. The MSP430 ULP FRAM portfolio includes a range of devices with FRAM, ULP 16-bit MSP430 CPUs and smart peripherals for a variety of applications. The ULP architecture showcases seven low-power modes optimized to extend battery life in high-energy applications.
2. Feature
1. Embedded Microcontrollers
– 16-bit RISC architecture with clock frequencies up to 16-MHz
– Wide supply voltage range from 3.6 V to 1.8 V (minimum supply voltage limited by SVS level, see SVS specification)
2. Optimized ultra-low power mode
– Active mode: approximately 100 µA/MHz
– Standby (LPM3 with VLO): 0.4 µA (typ)
– Real Time Clock (LPM3.5): 0.25 µA (typ)(1)
– Shutdown (LPM4.5): 0.02 µA (typ)
3. Ultra-low-power Ferroelectric RAM (FRAM)
– Up to 64KB of non-volatile memory
– Ultra low power write
– Fast writes of 125 ns per word (64KB in 4 ms)
– Unified Memory = Program + Data + Single Space Storage
– 1015 write cycle endurance
– Radiation resistant and non-magnetic
4. Smart digital peripherals
– 32-bit hardware multiplier (MPY)
– 3-channel internal DMA
– Real Time Clock (RTC) with calendar and alarm functions
– Five 16-bit timers, each with up to seven capture/compare registers
– 16-bit Cyclic Redundancy Checker (CRC)
5. High performance simulation
– 16-channel analog comparator
– 12-bit analog-to-digital converter (ADC) with internal reference and track-and-hold and up to 16 external input channels
6. Multi-function input/output ports
– Capacitive touch functionality on all pins, no external components required
– Accessible bits, bytes and words (in pairs)
– Edge-selectable LPM wakeup on all ports
– Programmable pull-ups and pull-downs on all ports
7. Code security and encryption
– 128-bit or 256-bit AES secure encryption and decryption coprocessor
– Random number seed for random number generation algorithm
8. Enhanced serial communications
– eUSCI_A0 and eUSCI_A1 support
– UART with automatic baud rate detection
– IrDA encoding and decoding
– SPI
– eUSCI_B0 support
– I2C with multiple slave addressing
– SPI
– Hardware UART and I2C Bootloader (BSL)
9. Flexible clock system
– Fixed frequency DCO with 10 selectable factory trimmed frequencies
– Low-power low-frequency internal clock source (VLO)
– 32kHz crystal (LFXT)
– High Frequency Crystal (HFXT)
10. Development tools and software
– Free professional development environment with EnergyTrace++™ technology
– Development Kit (MSP-TS430RGZ48C)
11. family member
– Device comparison summarizes available device variants and package types
12. For complete module descriptions, see MSP430FR58xx, MSP430FR59xx and MSP430FR6xx Family User Guide
3. Application
1. Metering
2. Energy harvesting sensor nodes
3. Wearable Electronics
4. Sensor management
5. data record
4. Pin configuration
5. Function description
1. Digital input/output
– All individual I/O bits are independently programmable.
– Any combination of input, output and interrupt conditions is possible.
– Programmable pull-ups or pull-downs on all ports.
– Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input functions are available for all ports.
– All instructions support read and write access to port control registers.
– Ports can be accessed in byte or word pairs.
– All pins of ports P1, P2, P3, P4, and PJ support capacitive touch I/O functionality.
– No cross current during startup.
2. Embedded Emulation Module
– Three hardware triggers or breakpoints for memory access
– A hardware trigger or breakpoint for CPU register write access
– Up to four hardware triggers can be combined to form complex triggers or breakpoints
– A cycle counter
– Block-level clock control
3. DMA controller
The DMA controller allows moving data from one memory address to another without CPU intervention. For example, a DMA controller can be used to move data memory to RAM from ADC12_B conversions. Using a DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without A wake-up is required to move data in or out of the peripheral.
4. CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registe rs are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.
