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1. Describe
SP3222E and SP3232ECN-L/TR series are RS-232 transceiver solutions Suitable for portable or handheld applications, such as laptops Or a handheld computer. SP3222E / SP3232ECN-L/TR series has a high-efficiency charge pump power supply that only requires 0.1µF The capacitor operates at 3.3V. This charge pump allows SP3222E / SP3232E series provide true RS-232 performance The power supply range is 3.0V to 5.5V. SP3222E / SP3232E It is a 2 drive/2 receiver device. This series is very suitable for portable or Handheld applications, such as laptops or handheld computers. this The ESD tolerance of SP3222E / SP3232E devices exceeds ±15kV Suitable for human body model and IEC61000-4-2 air discharge test method. SP3222E device has a low-power shutdown mode The driver output and charge pump of the device are disabled. During shutdown, the supply current drops below 1µA.
2. Feature
1. Conform to the true EIA/TIA-232-F standard 3.0V to 5.5V power supply
2. Minimum 120kbps data rate under full load
3. 1μA low-power shutdown receiver Active (SP3222E)
4. Interoperable with RS-232 as low as 2.7V Energy source
5. Enhanced ESD specification:
- ±15kV human body model
- ±15kV IEC61000-4-2 air discharge
- ±8kV IEC61000-4-2 contact freed
3. Pin configuration
4. Pin description
5. Applications Information
1. VSS charge storage
During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl + is then switched to GND and the charge in C1–is transferred to C2 –. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC.
2. VSS transfer
Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND.
3. VDD charge storage
The third phase of the clock is identical to the first phase; the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2 + is at VCC, the voltage potential across C2 is 2 times VCC.
4. VDD transfer
The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to 5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at greater than 250kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating.
